1. Field of the Invention
The present invention relates to a dummy word line driving circuit for a MOS dynamic RAM.
2. Description of the Prior Art
In a one-transistor type MOS dynamic RAM, whether a charge is stored or not in the MOS capacitor corresponds to the information "1" or "0".
The structure of a conventional memory array of a MOS dynamic RAM is shown in FIG. 3. In the figure, 1 denotes a memory cell composed of a memory capacitor having a capacitance of Cs and a MOS transistor. A voltage signal which is transmitted from the memory cell to a sense amplifier 2, namely, a signal voltage appears on a bit line BL or a bit line BL, is determined by the proportion of the amount of a signal charge Qs stored in the memory capacitor to the stray capacitance Cb of the bit line. Now, assuming that the voltage written in the memory capacitor is at the source voltage level Vcc(V) when the information is "1", and that the voltage is at the ground level 0(V) when the information is "0", the difference .DELTA.V between the signal voltage of "1"and "0" is represented as follows: .DELTA.V=Cs Vcc/(Cs+Cb). The information "1" or "0" is determined by a comparison between the signal voltage Vcc(V) or 0(V) and the reference voltage read out from a dummy cell 4 at the sense amplifier 2. Therefore, the dummy cell 4 is composed so as to employ a half of the capacitance value Cs/2 of the memory capacitor as a dummy capacitor, so that 0(V) is always written therein.
The operation of a conventional memory cell will be described with reference to the structure of FIG. 3 and a diagram of waveform in FIG. 4. First, one X decoder is selected from a plurality of X decoders 5 according to an address input, and one word line WL.sub.0 is selectively driven by a word driver 7 according to a signal .phi.X.sub.0, which is a sub-decoded signal of a word line driving signal .phi.X (here, description of one example will be given in which a word line WL.sub.0 is selected).
On this occasion, a dummy word line DWL.sub.0 is driven by a dummy word driver 9-2 simultaneously. Consequently, the information stored in the memory capacitor is transferred to the bit line BL, while the information stored in the dummy capacitor is transferred to the bit line BL. A subtle potential difference between the two is differentially amplified by the sense amplifier 2. An active restore circuit 10, which is connected to the sense amplifier 2, restores the dropped voltage of the bit line on the high-level side which is generated during the differential amplification to the level of the source voltage Vcc. Meanwhile, a signal .phi.DR is a dummy reset signal which writes 0(V) into the dummy capacitor, a signal .phi.WR is a word reset signal which discharges the voltage of the selectively driven word line at the end of the memory cycle.
In a conventional structure as described above, the capacitance of the dummy capacitor of the dummy cell 4 is required to be a half of the capacitance of the memory capacitor. Therefore, if a memory having a large memory capacity comes to be implemented by decreasing the size of each of the cells in a chip and thus increasing the number of cells in a chip, it will be difficult to lay out the dummy capacitors. In addition, the size of the dummy cell 4 defines the degree of integration of the memory, resulting in a drawback that it is obstructive to the implementation of a memory of high density.